I've got this giant net list of stuff that comes out of more or less the result of multilevel logic synthesis. And what's interesting is it takes what feels like a very complicated Boolean algebra kind of approach to a problem.
The problem is going to be solved in a style called tree covering. And we're actually going to show a very interesting model of the problem. So here in Lecture 10.2, we're going to continue to talk about technology mapping. Elementary knowledge of RC linear circuits (at the level of an introductory physics class). Linear algebra and calculus at the level of a junior or senior in engineering. An understanding of basic digital design: Boolean algebra, Kmaps, gates and flip flops, finite state machine design. Programming experience (C, C++, Java, Python, etc.) and basic knowledge of data structures and algorithms (especially recursive algorithms). Topics covered will include: technology mapping, timing analysis, and ASIC placement and routing. Our goal is for students to understand how the tools themselves work, at the level of their fundamental algorithms and data structures. Our focus in this part of the course is on the key logical and geometric representations that make it possible to map from logic to layout, and in particular, to place, route, and evaluate the timing of large logic networks. This class focuses on the major design tools used in the creation of an Application Specific Integrated Circuit (ASIC) or System on Chip (SoC) design. How do people manage to design these complicated chips? Answer: a sequence of computer aided design (CAD) tools takes an abstract description of the chip, and refines it step-wise to a final design. You should complete the VLSI CAD Part I: Logic course before beginning this course.Ī modern VLSI chip is a remarkably complex beast: billions of transistors, millions of logic gates deployed for computation and control, big blocks of memory, embedded blocks of pre-designed functions designed by third parties (called “intellectual property” or IP blocks).
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